Integrated circuit with stop layer and method of manufacturing the same

ABSTRACT

A method of manufacturing an integrated circuit is provided. According to the method, first and second stop layers are deposited on a first dielectric layer that covers a first metallization level. The second stop layer is selectively etched with respect to the first stop layer, and the first stop layer is selectively etched with respect to the first dielectric layer. A second dielectric layer and a third stop layer are deposited. The third stop layer is selectively etched with respect to the second dielectric layer, and the first and second dielectric layers are selectively etched with respect to the stop layers so as to form trenches in the second dielectric layer and holes in the first dielectric layer. Additionally, an integrated circuit is provided that includes first and second metallization levels. A dielectric layer is located between the metallization levels, and a first stop layer is located between the dielectric layer and the second metallization level. A second stop layer is located above the first stop layer, and a third stop layer is located above the dielectric material of the second metallization level. In one preferred embodiment, lines of at least one metallization levels are made of copper, and the dielectric layer is made of an organic polymer having an electrical permittivity coefficient of less than 3.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based upon and claims priority from priorFrench Patent Application No. 98-04754, filed Apr. 16, 1998, the entiredisclosure of which is herein incorporated by reference.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to integrated circuits, and morespecifically to a semiconductor integrated circuit having a stack ofconducting layers separated by insulating layers.

[0004] 2. Description of Related Art

[0005] In conventional integrated circuits, it is necessary to establishelectrical connections between conducting metallized layers that are ondifferent levels and separated by one or more insulating layers. Twoconducting layers are conventionally electrically connected using holesthat are provided in the insulating layer and filled with metal, such aconnection being known as a “via”. One way of producing such integratedcircuits is through a process known as the “Damascene” process. A firstinsulating layer is deposited on a metallization layer of level n. Theholes are etched through the insulating layer, and the metal for the viais deposited and polished until it is level with the upper surface ofthe insulating layer.

[0006] Then, a new insulating layer is deposited on the formed via oflevel n and the trenches for the lines are etched. The metal for thelines of the metallization layer of level n+1 is deposited, and thenpolished until level with the upper surface of the insulating layer. TheDamascene process is well suited for producing copper lines and viasbecause, although copper has advantageous electrical properties fornarrow lines, it cannot be etched at ambient temperature. Additionally,the Damascene process can be used with the metals more commonly used toform lines and vias.

[0007] In a “double Damascene” process, the metal is deposited in boththe vias and the lines and then polished. A stop layer, usually made ofnitride, is provided between an insulating layer of level n and themetallization level n+1. In order to obtain the final structure, theremust be excellent etching selectivity for the oxide of the insulatinglayer with respect to the nitride.

[0008] In order to increase the density of integrated circuits, attemptshave been made to reduce the width of the metal lines and of thedielectric material separating metal lines. However, the electricalcapacitance between two adjacent metal lines is inversely proportionalto the distance separating them. Thus, by reducing this distance toincrease the density of the circuit, the interline capacitance isincreased. This is a problem because it causes an increase in thepropagation constant of the electrical signal in the lines, τ=RC (Rbeing the resistance of the metal line and C being the interlinecapacitance), as well as in an increase in the parasitic couplingbetween two electrical signals propagating in two adjacent lines (i.e.,the crosstalk effect).

[0009] The interline capacitance is proportional to the permittivitycoefficient “k” of the dielectric material that is used, so there is atendency to use dielectric materials having a low permittivitycoefficient “k”. For example, dielectric organic polymers havingpermittivity coefficients more than 30% lower than the typical siliconoxide SiO₂ can be used. However, these organic polymers create etchingproblems because their chemical composition is close to that of theresin mask that is used to photo-etch the trenches. More specifically,the resin mask is removed by an isotropic etching in which the etchingions move in all directions. This can cause the organic polymer thatserves as the dielectric to be impaired, or even etched. A similarproblem results from the use of a dielectric made from an inorganicpolymer whose surface becomes impaired so as to locally degrade thepermittivity coefficient.

SUMMARY OF THE INVENTION

[0010] In view of these drawbacks, it is an object of the presentinvention to remove the above-mentioned drawbacks and to provide aDamascene-type process for manufacturing an integrated circuit using adielectric having a low permittivity coefficient. According to theprocess, first and second stop layers are deposited on a firstdielectric layer that covers a first metallization level, and the secondstop layer is selectively etched with respect to the first stop layer.The first stop layer is selectively etched with respect to the firstdielectric layer, a second dielectric layer is deposited on the circuit.The first and second dielectric layers are selectively etched withrespect to the stop layers. In this manner, trenches are formed in thesecond dielectric layer and holes are formed in the first dielectriclayer. Thus, a dielectric made of an organic or inorganic polymer havinga low permittivity coefficient can be used without causing degradation,and low interline capacitances can be obtained.

[0011] In one preferred method, a third stop layer is deposited on thesecond dielectric layer. The third stop layer is selectively etched withrespect to the second dielectric layer.

[0012] In one preferred method, after the trenches and holes are formed,metal is deposited in the holes and trenches to form the lines of asecond metallization level and vias connecting the lines of first andsecond metallization levels. Then, the metal of the lines of the secondmetallization level is polished. In another preferred method, anencapsulation layer (e.g., of silicon nitride) is placed around themetal lines. The encapsulation layer is useful when the metal used forthe lines is of a type that could diffuse into the dielectric. Suchdiffusion of metal (especially of copper or gold) into the dielectricwould result in a decrease in the interline electrical isolation. Themajor risk is that the metallic contamination could reach the siliconsubstrate to create deep energy levels in the band gap of thesemiconductor and increase the resistivity of the substrate.

[0013] Another object of the present invention is to provide anintegrated circuit in which the dielectric layer is of a type that wouldconventionally be impaired by the etching process for removing the resinmask that is used to photo-etch the positions of the metallizationlines. The integrated circuit includes at least first and secondmetallization levels that each include metallization lines separated bydielectric material. A dielectric layer is located between the twometallization levels and penetrated by vias that provide electricalconnection between the metallization lines of the two metallizationlevels. A first stop layer, which is capable of being selectively etchedwith respect to the dielectric layer, is located between the dielectriclayer and the second metallization level. Additionally, a second stoplayer, which is capable of being selectively etched with respect to thefirst stop layer, is located above the first stop layer. The stop layersare provided because the mask used for photo-etching is of a similarnature to the polymers having a low permittivity coefficient, which aredesirable (especially organic polymers) but would conventionally beimpaired during removal of the mask.

[0014] Preferably, a third stop layer, which is capable of beingselectively etched with respect to the dielectric material of the secondmetallization level, is located above the dielectric material of thesecond metallization level.

[0015] Accordingly, preferred embodiments of the present inventionprovide an integrated circuit that can have very small line widths andvery small interline widths of dielectric material because thedielectric used has a low permittivity coefficient but is not degradedduring the Damascene-type process for forming the circuit.

[0016] Other objects, features, and advantages of the present inventionwill become apparent from the following detailed description. It shouldbe understood, however, that the detailed description and specificexamples, while indicating preferred embodiments of the presentinvention, are given by way of illustration only and variousmodifications may naturally be performed without deviating from thepresent invention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0017]FIGS. 1a through 1 g show steps of a conventional double Damasceneprocess;

[0018]FIGS. 2a through 2 c show steps of a conventional double Damasceneprocess using a dielectric made of an organic polymer; and

[0019]FIGS. 3a through 3 h show steps of an integrated circuitmanufacturing process according to a preferred embodiment of the presentinvention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0020] Preferred embodiments of the present invention will be describedin detail hereinbelow with reference to the attached drawings.

[0021] As shown in the cross-sectional drawing of FIG. 1a, an integratedcircuit includes metal lines 1 of a metallization level n that areseparated by a dielectric material 2. The metallization level n iscovered with a dielectric layer 3 (e.g., a silicon oxide having apermittivity coefficient on the order of 4) of the same nature as thedielectric material 2. The dielectric layer 3 is covered with a stoplayer 4 having a chemical composition that is slightly different so asto allow it to be selectively etched with respect to the dielectriclayer 3. The stop layer 4 is partially covered by a mask 5 forphoto-etching.

[0022] The stop layer 4 is selectively etched with respect to thedielectric layer 3 and with respect to the mask 5 as shown in FIG. 1b,and then the mask 5 is removed as shown in FIG. 1c. The removal of themask has no effect on the dielectric layer 3 because the composition ofthe mask 5 differs from that of the dielectric layer 3. Next, as shownin FIG. 1d, the circuit is covered with dielectric material 6 andanother mask 7. The dielectric material 6 and the dielectric layer 3 areselectively etched with respect to the mask 7 and the stop layer 4 so asto define holes 8 that penetrate the dielectric layer 3 and trenches 9that penetrate the dielectric material 6, as shown in FIG. 1e.

[0023] Then, as shown in FIG. 1f, the mask 7 is selectively removed withrespect to the dielectric material 6 and the dielectric layer 3 in thesame manner as the mask 5. As shown in FIG. 1g, the holes 8 and trenches9 are filled with metal so that the holes 8 filled with metal form viasbetween metallization levels n and n+1 and the trenches 9 filled withmetal form the lines of metallization level n+1. While the process ofFIGS. 1a through 1 g can be used to form an integrated circuit, such aprocess is not suitable for manufacturing circuits using dielectricmaterials having a low permittivity coefficient, as will now beexplained with reference to FIG. 2.

[0024]FIGS. 2a through 2 c show the same processing steps as shown inFIGS. 1a through 1 c, but different dielectric materials are used. InFIGS. 2a through 2 c, the dielectric material 10 separating themetallization lines 1 and the dielectric layer 11 are both made from adielectric having a low permittivity coefficient of the organic polymertype, and the stop layer 4 is provided to allow selective etching withrespect to the dielectric layer 11. As shown in FIG. 2c, the process forremoving the mask 5 is not selective with respect to the dielectriclayer 11. Thus, holes 12 are formed of a shape that is absolutelyuncontrollable because the etching process used to remove the mask 5 isof the isotropic type (i.e., it etches the material in all directions).If metal were to be deposited in the holes 12, unsatisfactory electricalisolation and a high capacitance between the vias would result. Thus, anintegrated circuit having unacceptable characteristics would beproduced.

[0025]FIGS. 3a through 3 h show a process according to a preferredembodiment of the present invention that allows a dielectric having alow permittivity coefficient (of the inorganic or organic type) to beused in a Damascene-type process. As shown in FIG. 3a, the integratedcircuit includes a metallization level n having metallized lines 20(e.g., made of copper) that are separated by a dielectric 21. Themetallization level n is covered with a dielectric layer 22 that is madewith the same low permittivity coefficient material as the dielectric21, such as one of the inorganic type known as “Fox” having apermittivity coefficient of 3 or one of the organic type known as “Silk”having a permittivity coefficient of 2.6. (The latter being preferablebecause it can be used in thick layers of for example 2 μm, unlike theinorganic dielectric which is limited to 0.7 μm. This drawback is addedto that of having a slightly higher permittivity coefficient.)

[0026] The dielectric layer 22 is covered with a first stop layer 23 anda second stop layer 24. The first stop layer 23 is of a composition thatcan be selectively etched with respect to the dielectric layer 22, andthe second stop layer 24 is of a composition that can be selectivelyetched with respect to the dielectric layer 22 and the first stop layer23. The second stop layer 24 is covered with a mask 25 forphoto-etching. Next, as shown in FIG. 3b, the second stop layer 24 isselectively etched with respect to the mask 25 and the first stop layer23 so that those portions of the second stop layer 24 that are notcovered by the mask 25 are removed (because of their exposure to theetching process).

[0027] As shown in FIG. 3c, the mask 25 is then removed selectively withrespect to the second stop layer 24 and the first stop layer 23 using anoxygen-rich plasma. At this stage, the dielectric layer 22 is completelyprotected by the first stop layer 23. Next, as shown in FIG. 3d, thefirst stop layer 23 is selectively etched with respect to the secondstop layer 24 and the dielectric layer 22. As shown in FIG. 3e, anadditional dielectric layer 26 is then deposited on the integratedcircuit. The additional dielectric layer 26 can be made of the samematerial as the dielectric layer 22. The additional dielectric layer 26is then covered with a third stop layer 27 that can be selectivelyetched with respect to the additional dielectric layer 26, and with amask 28 for photo-etching.

[0028] The third stop layer 27 is selectively etched with respect to themask 28 and the additional dielectric layer 26, as shown in FIG. 3f,with those portions of the third stop layer 27 that are protected by themask 28 remaining in place while the other portions are removed by theetching. As shown in FIG. 3g, the additional dielectric layer 26 and thedielectric layer 22 are etched in a selective way with respect to thethird stop layer 27 and the second stop layer 24 to form trenches 29 inthe additional dielectric layer 26 and holes 30 in the dielectric layer22 and the first and second stop layers 23 and 24. Because this etchingoperation must be selective with respect to the second and third stoplayers 24 and 27, they can be made of the same material (e.g., siliconoxide SiO₂ or silicon oxynitride SiON).

[0029] Further, in one embodiment, a first stop layer made of siliconoxynitride SiON or silicon nitride SiN is provided. In anotherembodiment, a first stop layer made of silicon nitride is provided. Itis also possible to use first and second stop layers whose compositionis the reverse of that explained above, or a third stop layer of acomposition different from that of the second. It is preferable to use athin (e.g., 200 to 300 Å) silicon nitride layer because of its highpermittivity coefficient. A silicon oxide layer may be thicker (e.g.,1000 Å) because of a more satisfactory permittivity. A layer ofoxynitride SiON may be advantageously employed because of itsantireflective characteristics that prevent a change in hole size duringphoto-etching. The thickness of this layer with respect to thewavelength of the light that is used can be optimized to prevent themask from being etched at the edges of the holes.

[0030] After the trenches 29 and holes 30 have been etched, they arefilled with metal to form vias 31 in the holes 30 and lines 32 in thetrenches 29, and thus the metallization level n+1. The process can thenbe repeated to form an integrated circuit having more than twometallization levels. During removal of the mask 25, the dielectriclayer 22 is protected by the presence of two stop layers, the second ofwhich was subjected to an etching operation that marks the futurepositions of the vias. When etching the trenches 29 and holes 30, theintegrated circuit is electrically biased so that the trajectory of theions that perform the etching is vertical, in order to etch the materialin only the vertical direction (e.g., to effect anisotropic etching).

[0031] During this etching, the mask 28 placed on the third stop layer27 is rapidly consumed by the plasma ions that strike the surface of theintegrated circuit at the points where the mask 28 is located. Theremoval of the mask 28 and the etching of the trenches 29 and holes 30are therefore carried out simultaneously. Importantly, this anisotropicetching does not affect those portions of the dielectric layer 22 andthe additional dielectric layer 26 that are protected by the variousstop layers. Thus, it is possible to obtain suitably shaped trenches 29and holes 30 while maintaining an approximately constant thickness ofdielectric material between them.

[0032] In a preferred embodiment, the metallization lines are made ofcopper or gold, and the dielectric layer is made of an organic polymerhaving an electrical permittivity coefficient of less than 3 (e.g., a“Silk” polymer having a coefficient k of 2.6). Further, in preferredembodiments, the dielectric material of the metallization levels isidentical to that of the dielectric layer. In one preferred embodiment,the first stop layer is made of silicon nitride or silicon oxynitride,and the second stop layer is made of silicon oxide. In preferredembodiments, there is either: a first stop layer made of silicon nitrideand a second stop layer made of silicon oxide, or a first stop layermade of silicon nitride and a second stop layer made of siliconoxynitride, or a first stop layer made of silicon oxynitride and asecond stop layer made of silicon oxide. The third stop layer is made ofone of these three materials.

[0033] Accordingly, the present invention provides a Damascene-typeprocess for manufacturing an integrated circuit with dielectric layershaving a low permittivity coefficient. Thus, copper lines and vias canbe produced with small etching widths and the integration density of theintegrated circuit can be increased.

[0034] While there has been illustrated and described what are presentlyconsidered to be the preferred embodiments of the present invention, itwill be understood by those skilled in the art that various othermodifications may be made, and equivalents may be substituted, withoutdeparting from the true scope of the present invention. Additionally,many modifications may be made to adapt a particular situation to theteachings of the present invention without departing from the centralinventive concept described herein. Furthermore, embodiments of thepresent invention may not include all of the features described above.Therefore, it is intended that the present invention not be limited tothe particular embodiments disclosed, but that the invention include allembodiments falling within the scope of the appended claims.

What is claimed is:
 1. A method of manufacturing an integrated circuit,said method comprising the steps of: depositing first and second stoplayers on a first dielectric layer that covers a first metallizationlevel; selectively etching the second stop layer with respect to thefirst stop layer; selectively etching the first stop layer with respectto the first dielectric layer; depositing a second dielectric layer onthe circuit, and selectively etching the first and second dielectriclayers with respect to the stop layers so as to form trenches in thesecond dielectric layer and holes in the first dielectric layer.
 2. Themethod as defined in claim 1, further comprising the steps of:depositing a third stop layer on the second dielectric layer;selectively etching the third stop layer with respect to the seconddielectric layer;
 3. The method as defined in claim 1, furthercomprising the steps of: after depositing the first and second stoplayers, depositing a first mask on the second stop layer; and afterdepositing the third stop layer, depositing a second mask on the thirdstop layer.
 4. The method as defined in claim 3, wherein in the step ofselectively etching the first and second dielectric layers, the secondmask is removed simultaneously with the forming of the trenches andholes.
 5. The method as defined in claim 3, wherein the first and secondmasks are resin masks.
 6. The method as defined in claim 1, furthercomprising the step of depositing metal in the holes and trenches toform a second metallization level and vias connecting the first andsecond metallization levels.
 7. The method as defined in claim 6,wherein each of the first and second metallization levels includesmetallization lines separated by dielectric material.
 8. The method asdefined in claim 7, further comprising the step of etching a layer forencapsulating the metallization lines of the second metallization level.9. The method as defined in claim 1, further comprising the step ofetching a layer for encapsulating lines of a second metallization level.10. An integrated circuit comprising: at least first and secondmetallization levels, each of the metallization levels includingmetallization lines separated by dielectric material; a dielectric layerlocated between the first and second metallization levels, thedielectric layer being penetrated by vias that electrically connect themetallization lines of the first and second metallization levels; afirst stop layer located between the dielectric layer and the secondmetallization level, the first stop layer being selectively etchablewith respect to the dielectric layer; and a second stop layer locatedabove the first stop layer, the second stop layer being selectivelyetchable with respect to the first stop layer.
 11. The integratedcircuit as defined in claim 10, further comprising a third stop layerlocated above the dielectric material of the second metallization level,the third stop layer being selectively etchable with respect to thedielectric material of the second metallization level.
 12. Theintegrated circuit as defined in claim 10, wherein the metallizationlines of at least one of the first and second metallization levels aremade of copper.
 13. The integrated circuit as defined in claim 11,wherein the dielectric layer is made of an organic polymer having anelectrical permittivity coefficient of less than
 3. 14. The integratedcircuit as defined in claim 10, wherein the dielectric layer is made ofan organic polymer having an electrical permittivity coefficient of lessthan
 3. 15. The integrated circuit as defined in claim 10, wherein thedielectric material of the first and second metallization levels is thesame as the material of the dielectric layer.
 16. The integrated circuitas defined in claim 10, wherein the first stop layer is made of siliconnitride.
 17. The integrated circuit as defined in claim 15, wherein thesecond stop layer is made of silicon oxide.
 18. The integrated circuitas defined in claim 15, wherein the second stop layer is made of siliconoxynitride.
 19. The integrated circuit as defined in claim 10, whereinthe first stop layer is made of silicon oxynitride.
 20. The integratedcircuit as defined in claim 18, wherein the second stop layer is made ofsilicon oxide.
 21. The integrated circuit as defined in claim 10,wherein the second stop layer is made of silicon oxide.
 22. Theintegrated circuit as defined in claim 10, wherein the third stop layeris made of silicon nitride, silicon oxide, or silicon oxynitride. 23.The integrated circuit as defined in claim 10, further comprising alayer for encapsulating the metallization lines of the secondmetallization level.
 24. An information handling system including atleast one semiconductor device that contains an integrated circuit, saidintegrated circuit comprising: at least first and second metallizationlevels, each of the metallization levels including metallization linesseparated by dielectric material; a dielectric layer located between thefirst and second metallization levels, the dielectric layer beingpenetrated by vias that electrically connect the metallization lines ofthe first and second metallization levels; a first stop layer locatedbetween the dielectric layer and the second metallization level, thefirst stop layer being selectively etchable with respect to thedielectric layer; and a second stop layer located above the first stoplayer, the second stop layer being selectively etchable with respect tothe first stop layer.
 25. The information handling system as defined inclaim 24, further comprising a third stop layer located above thedielectric material of the second metallization level, the third stoplayer being selectively etchable with respect to the dielectric materialof the second metallization level.
 26. The information handling systemas defined in claim 24, wherein the metallization lines of at least oneof the first and second metallization levels are made of copper.
 27. Theinformation handling system as defined in claim 24, wherein thedielectric layer is made of an organic polymer having an electricalpermittivity coefficient of less than 3.